Field programmable gate arrays (FPGAs) are becoming increasingly popular devices for use in electronics systems. For example, communications systems employ FPGAs in large measure for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because they permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility in their re-programmability.
Programmable logic blocks are central to the capabilities of FPGAs. An FPGA typically is implemented with an array of programmable logic blocks that are configurable to implement design-specific logic functions. The interconnections between programmable logic blocks are also configurable.
Advances in integrated circuit technology support implementing an increasing number of functions in a smaller area. This has allowed FPGAs to be designed with programmable logic blocks with additional built-in features. For example, programmable logic blocks in the of the Virtex II FPGA from Xilinx are configurable to support shift register and RAM functions.
Even though the feature-rich programmable logic blocks provide a great deal of added flexibility, in many cases a design will use only a small portion of the built-in functions. The added built-in features are thereby provided at the expense of wasted circuit space.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.